74AS00 Quad 2-Input NAND Gate. Physical Dimensions inches (millimeters) unless otherwise noted (Continued). Lead Plastic Dual-In-Line Package ( PDIP). 74AS00 Datasheet, 74AS00 PDF, 74AS00 Data sheet, 74AS00 manual, 74AS00 pdf, 74AS00, datenblatt, Electronics 74AS00, alldatasheet, free, datasheet. description. These devices contain four independent 2-input positive-NAND gates. They perform the Boolean functions Y = A • B or Y = A + B in positive logic.
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Only one driver must be enabled at any time otherwise a conflict will occur. Problem 10 What is meant by negative logic?
datasheer That is, from Ohm’s Law one talks about 1 volt across 1 ohm produces 1 ampere. An open-collector output has current sinking capabilities, that is, it can present a logic-LO output. Digital logic is implemented using integrated circuits which are classified into families based on their basic electronic structure. Digital IC manufacturers are continually trying to minimize the delay-power product and continue to produce families with different characteristics to suit specific needs.
Regardless of the IC’s complexity or how dztasheet is created, basic knowledge of gates and flip-flops is still essential. What is the minimum and maximum values of R and C? This is called the high impedance or Hi-Z state. What is the voltage range that would be considered a logic LO? Complex electronic circuits for high volume production are produced today datqsheet ASICs application specific ICs compiled entirely using a computer-aided design CAD system. At any time, only one of the two switches is closed while the other is open.
The final chip may either be burned on the spot using a programmable logic array PLA or may be produced in higher volumes by the IC manufacturer. Within the TTL family, there are many second-generation families, each with different operating characteristics.
Let us examine the typical totem-pole output once again. What are the criteria for determining the value of the pull-up resistor for an open collector output? Observe here that the circuit elements associated with Q4 in the totem-pole circuit are missing and the collector of Q3 is left open-circuited, hence the name open-collector. Bus drivers with tri-state outputs are connected together to create a bus system.
This is useful for creating a party-line data bus or control bus whereby any one of several circuits may pull the line LO without causing damage to another active output.
Also shown in Figure 6. Construct the circuit shown and study how the frequency and duty cycle are affected by R2 and C. In other words, when Q3 is closed, Q4 is open.
How is the frequency affected by values of R and C? All simulation and debugging is conducted on the computer before the chip is created. Measure both the input voltage and the logic output of the inverter. Study the feedback circuits shown and use the oscilloscope to examine the signal at different stages in the circuit. Does this input constitute a logic LO or logic HI input?
Problem 7 – Schmitt trigger oscillator Construct this simple oscillator and measure the frequency of oscillation for a given R and C. What is the diference between a inverter and a Schmitt trigger? Problem 8 – Timer The timer IC is a popular circuit for 74ax00 asymmetric rectangular waves. Datadheet happens when the outputs of two totem-pole outputs are connected together?
Analyze the circuits and explain the results. The following table is a growing list of various sub-families with their characteristics and designations.
What is the input hysteresis in volts for these two gates? Construct and test this circuit. In contrast with a normal datashedt output, it cannot be the source of current and therefore cannot present a logic-HI on its own. Families can be characterized by the relationship between propagation-delay and power. This configuration with Q4 stacked on top of Q3 is referred to as a totem-pole output. Outputs of several open-collector gates may be directly wired together to form a wired-OR logic function for negative logic.
From the measurements taken determine the propagation delay of a typical gate. Another common structure is CMOS complementary metal-oxide-silicon technology which exhibits low power and high noise immunity.
These two tend to be directly related, i. Using a very high frequency clock input measure the propagation delay of a typical 74xx or 74LSxx TTL gate. What is the minimum and maximum frequency of oscillation?